1. Field of the Invention
This invention relates generally to computer timing systems and more particularly to a phase lock oscillator for generating clock pulses which are locked to an incoming data stream.
2. Description of the Prior Art
There are two major types of read data recovery systems in use as follows:
1. all digital; and PA1 2. phase-locked loop "PLL".
In all digital recovery systems the ROM and various registers and counters are utilized to generate the clock from the data stream. This system has the advantage that no adjustments are required during manufacturing. However, the system can only tolerate changes in frequency of approximately .+-.1% or .+-.2%. This deficiency places a severe constraint on system design particularly with floppy disk drives of the five and one-quarter inch type since speed variations in excess of 1% and 2% are frequently encountered.
The phase lock loop type of read data recovery system however has the advantage that frequency variations of .+-.5% to .+-.8% can easily be tolerated. Additionally, the loop parameter design can easily be optimized by varying the filter characteristics. However the PLL has the disadvantage that it requires multiple power supply voltages in various portions of its circuit. For example, .+-.5 volts is required for the digital portion and a .+-.12 volts is required for the operational amplifier portion. Furthermore, the PLL requires a potentiometer adjustment during manufacturing to compensate for component tolerances.
What is needed, therefore, is a read recovery data system which can accommodate wide frequency variations and at the same time can be manufactured with fewer components and which utilizes a single voltage power supply.